1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same.
2. Description of the Background Art
In the past several years, intensive efforts have been taken to reduce the size of interconnections and provide multilayers for the purpose of further increasing the integration density of semiconductor integrated circuit devices. An interlayer insulation film is provided between each interconnection to obtain a multilayer structure of the interconnection. If the surface of this interlayer insulation film is not planar, a step-graded portion will be generated at the interconnection formed above the interlayer insulation film. This will cause defects such as disconnection. Therefore, the surface of the interlayer insulation film (the surface of the device) must be made as flat as possible. The technique to planarize the surface of the device is called planarization. This planarization technique has become ever important in reducing the size and providing multilayers of the interconnection.
In planarization, an SOG (Spin-On-Glass) film is known as an interlayer insulation film that is generally used. Recently, development in the planarization technique talking advantage of the flow of the interlayer insulation film material is particularly noticeable.
An xe2x80x9cSOGxe2x80x9d is the generic term of a film mainly composed of a solution in which a silicon compound is dissolved in an organic solvent, and silicon dioxide formed from that solution.
In forming an SOG film, first a solution having a silicon compound dissolved in an organic solvent is applied in droplets on a rotated substrate. By this rotation, the solution coating is provided so as to alleviate the step-graded portion on the substrate corresponding to the interconnection. More specifically, the coating is formed thick at the concave portion and thin at the convex portion on the substrate. As a result, the surface of the solution coating is planarized.
Then, heat treatment is applied to vaporize the organic solvent. Also, polymerization proceeds to result in a planarized SOG film at the surface.
An SOG film is typically classified into an inorganic SOG film that does not include any organic component in a silicon compound, as represented by the following general formula (1), and an organic SOG film including an organic component in a silicon compound, as represented by the following general formula (2).
[SiO2]nxe2x80x83xe2x80x83(1)
[RxSiYOZ]nxe2x80x83xe2x80x83(2)
(n, X, Y, Z: integer; R: alkyl group or aryl group)
Inorganic and organic SOG films have superior flatness. However, the inorganic SOG film includes a great amount of moisture and hydroxyl group. Therefore, it may adversely affect the metal interconnection and the like. There is the possibility of inducing problems such as degradation in electrical characteristics as well as corrosion. A similar, though less susceptible, problem is seen in an organic SOG film. This is because the organic SOG film includes some amount of moisture and hydroxyl group.
To compensate for this disadvantage when an SOG film is employed as an interlayer insulation film, an insulation film such as a silicon oxide film formed by, for example, plasma CVD, having the characteristics of insulation and mechanical strength in addition to the property of blocking moisture and hydroxyl group is provided between the SOG film and the metal interconnection (refer to Japanese Patent Laying-Open No. 5-226334, for example).
The provision of an insulation film such as a silicon oxide film formed by plasma CVD as in the conventional case between an SOG film and a metal interconnection will limit the decrease between the patterns of the underlying metal interconnection to bar the microminiaturization of the elements.
An object of the present invention is to provide a semiconductor device of superior reliability and suitable for microminiaturization, and a method of fabricating such a semiconductor device.
A method of fabricating a semiconductor device according to the present invention includes the steps of forming a first insulation film on a substrate, introducing impurities into the first insulation film, and embedding and forming a first conductive layer in the first insulation film. In a preferable embodiment, the step of forming a first conductive layer includes the step of embedding the first conductive layer in the first insulation film so that the surface of the first conductive layer is exposed. The method of this preferable embodiment further includes the steps of forming a second insulation film on the first insulation film, forming a contact hole in the second insulation film to expose a portion of the first conductive layer, and forming a second conductive layer in the contact hole, electrically connected to the first conductive layer. This method further desirably includes the step of introducing impurities into the second insulation film.
Another method of a preferable embodiment includes, after formation of the second insulation film and before formation of the contact hole, the steps of forming a first mask pattern on the second insulation film, forming a third insulation film on the second insulation film and on the first mask pattern, forming a second mask pattern having an opening larger than the first mask pattern on the third insulation film, etching the third insulation film using the second mask pattern to form a trench in the third insulation film arriving at the first mask pattern. In this method, the step of forming a contact hole includes the step of etching the second insulation film using the first mask pattern, and the step of forming a second conductive layer includes the step of forming a third conductive layer electrically connected to the second conductive layer in the trench, in addition to the formation of the second conductive layer.
Preferably, this method further includes the step of introducing impurities into the third insulation film.
A further method of a preferable embodiment further includes the step of forming a fourth insulation film on the substrate, prior to formation of the first insulation film. In this method, the step of introducing impurities into the first insulation film is carried out under the condition where the impurities arrive at the interface between the first insulation film and the fourth insulation film.
Preferably, the first insulation film includes a silicon oxide film containing at least 1% of carbon. Also preferably, the second insulation film includes a silicon oxide film containing at least 1% of carbon. Also preferably, the third insulation film includes a silicon oxide film containing at least 1% of carbon. Also preferably, the first insulation film includes an inorganic SOG film.
A still another method of a preferable embodiment includes, after formation of the second insulation film and before formation of a contact hole, the steps of forming a third mask pattern on the second insulation film, etching the second insulating film using the third mask pattern to selectively reduce the thickness of the second insulation film, and forming a fourth mask pattern on the second insulation film so as to expose a portion of the region reduced in thickness. In this method, the method of forming a contact hole includes the step of etching the second insulation film using the fourth mask pattern. The step of forming the second conductive layer includes the step of forming a third conductive layer electrically connected to the second conductive layer on the region that is reduced in thickness, in addition to the formation of the second conductive layer.
Yet a further method of a preferable embodiment includes the steps of forming a second insulation film on the first insulation film, forming a fifth mask pattern on the second insulation film, etching the second insulation film using the fifth mask pattern to form a contact hole in the second insulation film so as to expose a portion of the first conductive layer, forming a resist film in the contact hole and on the second insulation film after the fifth mask pattern is removed, patterning the resist film on the second insulation film to form a sixth mask pattern on the contact hole having an opening larger than the contact hole, etching the second insulation film using the sixth mask pattern to selectively reduce the thickness of the second insulation film, removing the resist pattern remaining in the contact hole and the sixth mask pattern, and forming a second conductive layer electrically connected to the first conductive layer in the contact hole.
In a preferable embodiment, the method further includes the step of introducing impurities into the second insulation film prior to formation of the contact hole in the second insulation film.
By introducing impurities into the first insulation film, the second insulation film and the third insulation film, respective films are modified in nature so that the moisture and hydroxyl group included in the films are reduced. Also, the film becomes less hygroscopic. Accordingly, the insulative property of the insulation film can be improved.
Particularly, by introducing impurities into the first, second, and third insulation films prior to formation of the first interconnection (conductive layer), the second interconnection (conductive layer) and the third interconnection (conductive layer), respectively, the impurities can be implanted to a depth substantially uniform over the entire film. Respective films can be modified uniformly.
By forming a fourth insulation film under the first insulation film in advance and introducing impurities into the first insulation film under the condition where the impurities reach the interface between the first and fourth insulation films, the intensity of adherence between the first insulation film and the fourth insulation film can be improved.
A semiconductor device according to the present invention includes a first conductive layer having a top face on a first plane, a first insulation layer introduced with impurities and having a top face on a second plane parallel to the first plane, a second insulation layer introduced with impurities and having a top face on a third plane parallel to the second plane, a second conductive layer embedded in the first insulation layer, and having a bottom in contact with the top face of the first conductive layer and a top face located on the second plane, and a third conductive layer embedded in the second insulation film, having a bottom in contact with the top face of the second conductive layer, and a top face located on the third plane.
In one embodiment, the second conductive layer and the third conductive layer are a single layer formed continuously.
In another embodiment, the first insulation layer and the second insulation layer are a single layer formed continuously. The second conductive layer and the third conductive layer are a single layer formed continuously.
Preferably, each of the first and second insulation layers includes an SOG film into which impurities are introduced by ion implantation.
In one embodiment, each of the first and second insulation layers includes a silicon nitride film on an SOG film.
In a preferable embodiment, a first conductive layer is embedded in a planarized insulation layer. Preferably, the insulation layer includes an SOG film into which impurities are introduced by ion implantation.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.